Signal routing device for a parallel transmission and/or switching network of coded signals

ABSTRACT

In a PCM switching network, a signal routing device is disclosed for diverting signals from a faulty section of the network to an emergency section. All the transmission paths included between the emergency section and the faulty section are shifted by one step towards the emergency section. At the outputs the reverse shift is performed.

I United States Patent 1 1 [111 3,865,991 Charransol et a1. Feb. 11, 1975 [54] SIGNAL ROUTING DEVICE FOR A 3,364,467 1/1968 Haibt 179/175.3 UX PARALLEL TRANSMISSION AND/OR 3,597,548 8/1971 Drinnan 179/15 AT SWITCHING NETWORK 0F CODED 3,603,736 9/1971 Morroll 179/15 BF SIGNALS OTHER PUBLICATIONS [75] Inventors: Pierre Charransol; Jacques Hauri,

both of Paris; Serge Robert Fontana, Lynch Catalog; Section 4, page 2002, Item B301; T1 Elancourt, all of France Span Line Switching System, Oct. 1, 1971.

[73] Assignee: International Standard Electric orp a i New York, Primary Examiner-David L. Stewart [22] Filed: June 28 1973 Attorney, Agent, or Firm-Delbert P. Warner; James B. Raden [21] Appl. No.: 374,312

[30] Foreign Application Priority Data [57] ABSTRACT July 13, 1972 France 72.25409 In a PCM switching network, a slgnal routing device 15 [52] CL" 179/15 BF ng/ls BY 179N753 R disclosed for diverting signals from a faulty section of 511 1m. 01. H04j 3/14 the "etwmk an emergemy the of Search..." R mission paths included between the emergency section 179/175'2 C 1753 1755 15 and the faulty section are shifted by one step towards the emergency section. At the outputs the reverse shift [56] References Cited 15 performed UNITED STATES PATENTS 2 Claims, 6 Drawing Figures 2,680,162 6/1954 Brehm 179/15 BF UX 8 65k RE 1 V fgca kgfl lgo2 P 03 j- -gel |-ge5 1 26 ge7 I I PE I -se5 se 6 -se 7 -se8 pf5 pf6 pf7 pf8- N5 Q8116 N7 M9 0' P P 0 E1 El VGEI 5 1 5 7 6" (SRO) (sm) (SR2) (s23 (SR4) (SR5) (SR6) (SR7) (SR8) PATENTED 3, 865,991

SHEET 1 BF 3 SRO (A) GE] (8) GEp Mn c5:

rMPI WEE F 5gp udO i i (A) as;

a GSp 1 SIGNAL ROUTING DEVICE FOR A PARALLEL TRANSMISSION AND/OR SWITCHING NETWORK OF CODED SIGNALS BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal routing device for a parallel transmission and/or switching network for coded signals and, more particularly, to a routing device provided for use with each input and output and making it possible to route at the input n signals on n among n l transmission and/or switching paths and to perform the reverse routing at the output. It is in particular serviceable in telephone exchanges employing time division switching of pulse code modulation signals.

2. Description of the Prior Art At the inputs of such an exchange, the signals from the lines are sampled at 8 kHz and each sample is converted into an 8-bit coded combination. Each 8-bit combination is transmitted in parallel on 8 conductors in a very short time constituting a channel time slot. It is possible to time-multiplex 256 channels for example. The recurring period of the successive combinations of a channel is 125 ts whereas the duration of each time slot is about 500 ns. An incoming multiplex group thus rotates the signals from 256 lines. A similar outgoing multiplex group routes the signals towards the same 256 lines. The above-mentioned numerical values, without being necessary, are nevertheless currently admitted.

Inside the exchange, it is necessary that a coded combination appearing on a time channel of a multiplex group be retransmitted on any time channel of any multiplex group. This entails space switching operations (connections from group to group) and time switching operations (connections from channel to channel). They will be carried out by means of a network including space switches and stores. This network may be, for example, of the well-known space-time-space type. A connection path between an incoming channel ofa first line (A) and an outgoing channel of a second line (B) uses two space switches arranged, in a way, on each side of a memory cell; they give it access, one to the incoming multiplex groups, the other to the outgoing multiplex groups. In this way, at the time slot assigned to the incoming channel and through the first switchorientated onto the appropriate incoming group, a coded combination originated from the incoming channel is stored in the memory cell. At the time slot assigned to the outgoing channel and through the second switch orientated onto the appropriate outgoing group, the coded combination originated from the incoming channel and kept in the memory cell is retransmitted on the outgoing channel. The connection in the opposite direction, between the outgoing channel of the first line (A) and the incoming channel of the second line (B) is carried out in the same way and uses generally the same memory cell.

In practice, the necessary numerous memory cells are memory cells belonging to several speech stores and two space switches are associated with each store. In a speech store, it is necessary to accede twice at least to each memory cell in a 125 as cycle, the first time, at the time slot assigned to the incoming channel and the second time, at the time slot assigned to the outgoing channel, each switch being accordingly orientated at these determined instants. The other cells of the same store make it possible to establish other calls, provided that they concern each time different time channels.

In such an exchange, the space switches are used, by time multiplexing, for a great number of calls. It is the same for the speech store common circuits and, in a general way, for all circuits transmitting and/or switching the coded combinations. A failure in any of these circuits will thus affect all the calls using the faulty circuit. This cannot be accepted.

The French Pat. application No. 71 07697 filed on Mar. 5, 1971 in the name of the Compagnie Ge'nrale de Constructions Tlphoniques entitled Rseau de transmission et/ou de commutation pour signaux code's (coded signal transmission and/or switching network) describes in a general way a switching network designed for obviating the effects of such a failure. This network provided for the parallel transmission and/or switching of coded signals, is constituted by the juxtaposition of several independent network sections each provided for transmitting and/or switching one single bit of the coded combinations in order that a failure, wherever it occurs, affects only one bit of the coded combinations, which both facilitates the detection of any failure and makes it possible to correct or minimize its effects.

Each switch is thus constituted by several independent elementary switches each one switching one bit of the coded combinations; these elementary switches are obviously parallel-controlled in order to have always the same orientation. Similarly, each store is constituted by several elementary stores, each storing one bit of the coded combinations; these elementary stores are parallel-controlled.

Moreover, if the coded combinations include n bits, the network includes at least n+l sections, whereas signal routing means are associated with the inputs and the outputs and make it possible to associate the n bits of each combination with n sections designated among the n+l networks sections. Therefore, if a failure occurs in any elementary unit transmitting the coded combinations, the concerned bit is routed onto an undamaged network-section.

SUMMARY OF THE INVENTION However, as each bit of the coded combinations must be able to be routed onto an emergency section, it is obvious that the emergency section does not present a transmission path identical to the others. Now, for propagation reasons, all paths provided must be practically identical, the system performances being determined by those of the worst transmission path. The present invention thus offers a particular routing mode making it possible to fulfil this condition and thus concerns generally a signal routing device for a parallel transmission and/or switching network of coded signals.

The routing device according to the invention has n signal accesses arranged according to a certain order and n+l network accesses also arranged according to a certain order and corresponding to n+l network sections. It includes normal switching means associating, in rest condition, the n signal accesses with the n network accesses of corresponding ranks, the n+lth network access of rank p corresponding to the emergency section network. It is mainly characterized in that it also includes switching means onto emergency provided for associating, in case of failure in one network section of rank m, the signal accesses of ranks m to p-l to the network accesses of ranks m+l to p, so that each signal access is connected either to the network access of same rank, at rest, or to the network access of the following rank, in case of failure, which modifies very little the transmission conditions of this signal.

According to another feature of the invention, the emergency network section occupies a central position of rank i and two groups of normal switching means associate, in rest condition signal accesses arranged from to i-l and from i+l to n with network accesses of same ranks, whereas two groups of switching means onto emergency are provided, those of the first group associating selectively the signal accesses of ranks O to i-l with the network accesses of ranks I to i, in case of failure in one of the network sections of ranks O to i-l and in the way previously described, those of the second group associating selectively the signal accesses of ranks i+l to n with the network accesses of ranks i to n-l in case of failure in one of the network sections of ranks i+l to n and in a mode symmetrical to the preceding one, which simplifies the design of the switching onto emergency control circuits.

BRIEF DESCRIPTION OF THE DRAWINGS Various other features will be disclosed from the following description given by way of non-limited example referring to FIGS. 1 to 6 which represent:

FIG. 1, the block schematic of a well-known time division switching network wherein may be applied the present invention;

FIG. 2, an illustration of the contents of store MTl and MP1 of FIG. 1; I

FIG. 3, an embodiment of the input equipment REl of FIG. 1, according to the invention;

FIG. 4, an embodiment of the output equipment RS1 of FIG. 1, according to the invention;

FIG. 5, an embodiment of the decoding circuits enabling the different control signals of FIGS. 3 and 4 to be obtained and FIG. 6, an embodiment of equipment REl of FIG. 3 enabling the routing of a possible check bit on the faulty section.

DESCRIPTION OF A PREFERRED EMBODIMENT First will be described referring to FIG. 1, the block schematic of the circuits of a switching network wherein may be applied the present invention.

This network includes incoming multiplex groups such as GEl. To each of them corresponds an outgoing multiplex group such as 681. Each multiplex group includes, for example, 256 time channels. To each time channel corresponds a channel time slot of about 500 us during which is transmitted a coded combination on several conductors in parallel. The recurring period of a same channel time slot is I25 us.

For the call establishment, several switching units are provided. For clarity reasons, in FIG. 1 there has been represented only one of them which includes a path store MTl, a speech store MP1, an incoming group switch CE1 and an outgoing group switch CS1.

All the units through which are transmitted the coded combinations, that is, in this case, the switches and the speech store, are made up of the juxtaposition of elementary units each transmitting one bit of the coded combinations. Thus, the switch CE1 is constituted by 9 elementary switches CEl to CEI identical and parallel-controlled. Each of them switches and transmits one bit, in a way totally independent of the others, so that a failure can only concern one bit at a time. Similarly, store MP1 is made up of 9 independent elementary stores MP1,, to MP1,, parallel-controlled and switch CS1 is constituted by 9 elementary switches CS1 to C81,.

It may be considered that the switching network is constituted by several network sections SRO to SR8, one network section including all the elementary units transmitting one bit of the coded combinations.

The path store MTl is a store having 256 cells cyclically read-out in synchronism with the multiplex group channel time slots. Each cell may contain an address of one cell of the speech store and a multiplex group number.

The speech store MP1 may have up to I28 memory cells which will be each assigned to one call. These memory cells are addressed according to information supplied by the path store MTl.

The switch CE1, during each channel time slot, associates the input of store MP1 to any incoming group, in response to the information supplied by a cell of the path store MTl.

The switch CS1, during each channel time slot, associates the output of store MP1 to any outgoing group. It always orientates in the same position as switch CE1.

The operation of this network will be described referring also to FIG. 2 and considering the case of a call between a subscriber (A) to which corresponds the channel time slot ID on the incoming and outgoing groups CE1 and G51, and another subscriber B to which corresponds the channel time slot 1] on the incoming and outgoing groups GEp and GSp.

At the channel time slot 0 a cell of the path store MTI supplies a group number G1 and an address adO. This number isv transmitted to switches CE1 and CS1, in parallel. In response, the latter orientate respectively onto groups GEl and GSl. Simultaneously the address ad0 is transmitted to the speech store MP1. In the latter the memory cell corresponding to this address is successively the object of a reading and writing operation.

The information read-out at the address ad() is transmitted to the multiplex group GSl, via switch CS1. Then, the information present on the multiplex group GEl, transmitted via switch CE1 to the input of the speech store MP1, is stored in-lieu of that just read out, at the address adO. Subscriber A has thus received a coded sample, whereas the one he supplied has just been recorded.

At the channel time slot tj a corresponding cell of path store MTl supplies the group number Gp and again, address adO. Switches CS1 and CE1 are accordingly orientated onto groups GEp and GSp. The address ad0 is transmitted to speech store MP1.

The information read-out at address adO is transmitted to the outgoing multiplex group GSp, via switch CS1. Then, the information present on the incoming multiplex group GEp, transmitted via switch CE1 to store MP1, is recorded at the address ad0. Subscriber B thus receives the coded sample previously received from subscriber A and recorded at time slot 10. The coded sample he supplies has just been recorded at adit is transmitted to subscriber A.

It can thus be seen that the considered call between two subscribers to which correspond different channel time slots and multiplex groups, necessitates the two path store cells corresponding to these channel time slots in the path store, one memory cell in the speech store and the use of switches CSI and CEI, at the appropriate time slots, in order to reach any multiplex group.

Moreover, in FIG. I are represented equipments REI and RS1 associated with groups GEI and GS]. Equipment REl receives the different bits of the coded combinations supplied in parallel by group GEI and retransmits them on conductors GEI to GEI Equipment RS1 receives the different bits of the coded combinations appearing on conductors GSI to GSI and supplies coded combinations transmitted in parallel on group GSl. In case of failure, equipments RE] and RS1 ensure the necessary switchings aswill be described hereafter. These means, according to the invention, make it possible to remedy to the effects of any failure occurring in the switching network circuits.

Indeed, as an illustration, if the coded combinations transmitted on the incoming and outgoing groups have 8 bits, whereas the switching network includes 9 sections SRO to SR8, equipment REI will route the 8 bits of the incoming combinations onto sections SRO to SR3 and SR5 to SR8; equipment RSI will supply the outgoing combinations by retransmitting the bits from said above sections. If a section fails, non-represented means will be provided which act upon equipments REI and RS1, as well as upon all identical equipments associated with the other multiplex groups, in order that these equipments route the 8 bits of the coded combinations onto the 8 undamaged network sections. These equipments thus enable, whichever is the network section where a failure has occurred, the routing of the coded combination bits onto the network sections in good condition whereas the faulty section is in a way isolated.

The network in FIG. I thus enables the routing of 8 bits in case of failure and of a 9th bit in the absence of failure. As the incoming and outgoing multiplex groups have 8 bits, the 9th network section (SR4) is not used in the absence of failure. However, equipment REI may advantageously add to the 8 bits of the multiplex group GEI a parity bit, whereas equipment RSI may include parity check means. The ninth network section (SR4) will be used for the routing of check bits helping to detect failures. In case of failure the 8 undamaged sections will be used for transmitting the 8 data bits, whereas the parity check will be disconnected until repair.

Now will be described referring to FIGS. 3 and 4, an embodiment of equipments RBI and RS1 of FIG. 1, according to the invention.

Conventionally, in the following description, the AND gates have been represented by a dot surrounded by a circle (symbol of logic intersection), the OR gates by a cross surrounded by a circle (symbol of logic union) and the bistables by two juxtaposed rectangles respectively containingdigits O and I; generally, the bistable inputs have not been represented and the outputs are located at the lower part of the rectangles.

Multiplex group GEI supplies the 8-bit coded combinations. Consequently, there has been provided, in

equipment REI of FIG. 3, a parity generator PEI delivering on its output conductors or signal accesses set) to se3 and seS to se8 the 8 bits of the coded combinations that it has received on its input conductors geO to ge7. It also delivers on its output conductor or parity access se4 a parity bit calculated from the preceding ones.

Equipment REI besides includes a set of 9 direct gates pe0 to pe8 enabling the transmission of the 9 bits provided by PEI on the conductors or network accesses GEI tfiEl Thus, gates pe0 to pe3 enabled by signals noted NO to N 3 connect the outputs set) to se3 of the parity generator PEI respectively toLl network accesses GEI to GEI when signals to N3 are present. It is the sam e for g ates pe5 to pe8 which, in presence of signals N5 to N8, connect the outputs se5 to se8 of the parity generator PEI respectively to the network accesses GEI to GEI Finally, gate pe4, in presence of condition N4, connects the output se4 of generator PEI to conductor GEI Equipment REI includes a set of eight transfer gates pfi) to pf3 and pjS to pfB. These gates are respectively controlled by signals referenced NO to N3 aENSB N8, complmentary of the respective signals NO to N3 andmto N8. These gates associate each output of the parity generator to the neighbouring network section. Indeed, when condition NT) disappears, thus when condition N0 is present, gate pfl) becomes conducting whereas gate pe0 becomes non-conducting; the bit of the coded combinations supplied by the parity generator PEI on its output set) is transmitted, through gate pfl), to conductor GEI and to th e network section SR1. Similarly, when condition N3 disappears, thus when condition N3 is present, gate pf3 associates the output se3 of generator PEI to the neighbouring sec tion SR4; condition NR is then cancelled.

In a symmetric way, in presence of condition N8, gate pf8 associates the output se8 of generator PEI to section SR7; when condition N5 is present, gate pfB associates the output se5 of generator PEI to the neighbouring section SR4, condition N4 being cancelled.

In conclusion gates pjD/3 associate respectively each signal access se0 to se3 with the neighbouring network section, according to a shift by one step towards the right, and gates pf5/8 associate respectively each signal access seS to se8 with the neighbouring section, according to a shift by one step towards the left.

As soon as a failure appears in network section SR3, condition N3 disappears and condition N3 appears. Condition N4 is removed. As above-seen, gates pe3 and pe4 are non-conducting and gate pf3 becomes conducting. Conductor GEI and section SR3 are isolated; the parity bit supplied by generator PEI on its output se4 is no longer transmitted to conductor GEl.,; the coded combination bit supplied by generator PEI on its output se3 is transmitted via gate pf3 and conductor GEI to the emergency section SR4.

Wheufailu e appears in network section SRO, con ditions NO to N3 as well as condition N4 disappear and conditions NO to N3 appear. Gates pe0 to pe4 are blocked and gates pfl) to pf3 become conducting. Conductor GEI and section SRO are isolated; the parity bit is no longer transmitted to conductor GEI,. The data bit supplied on output set) of generator PEI is transmitted, via gate pfl) and conductor GEI to section SR1; the data bit supplied on the' output sel is transmitted. via gate pjI and conductor GEI to section SR2 and so on up to the data bit supplied on the output se3 which is transmitted as previously, via gate pf3 and conductor GEI, to the emergency section SR4.

It is now assumed that a failure occurs in network s e ction SR5; condition N5 appears, conditions N4 and N5 disappear; gate pjS becomes conducting, gates p25 and pe4 are blocked. Conductor GEl and section SR5 are isolated; the parity bit supplied by generator PEI on its output ss4 is no longer transmitted to conductor GE1.,. The data bit supplied on the output 565 is transmitted via gate pfS and conductor GEL, to the emergency section SR4.

If it is finally assumed that a failure occurs in network section SR2; coniion N8 to N5 appear and conditions N4 and N8 to N5 disappear. Gates pe8 to pe4 are blocked and gates pf8 to pfS become conducting; condu ctor GEL, and s ection SR8 are isolated, the parity bit is no longer transmitted to conductor GEl,,. The data bit supplied on the output s28 is transmitted via gate pf8 and conductor GE1-,, to the network section SR7; the data bit supplied on the output se7 is transmitted via gate pf7 and conductor GEl to the network section SR6 and so on up to the data bit, supplied on the output seS, which is transmitted via gate pf5 and conductor GEL, to the emergency section SR4.

In the switching center of FIG. 1, as soon as a failure occurs, this shift by one step towards the emergency section, of all paths included between this emergency section and the faulty section, is carried out in all input equipments such as REl, as just described.

Now referring to FIG. 4, will be described an embodiment of the output equipment RS1.

Equipment RS1 includes a parity check circuit PS1 corresponding to circuit PEI (FIG. 3). This circuit retransmits on its output conductors ss to ss8 the bits received respectively on its input conductors GSl to G81 In case of parity error, this circuit supplies on a group of conductors ftl a combination which enables the identification of the faulty section.

Equipment RS1 includes moreover gates ps0 to ps3 and ps to ps8, for the direct transfer of the 8 coded combination bits, in the absence of failure, as well as transfer gates pt0 to pt3 and 12:5 to pt8. Gates pt0 to pt3 and pt5 to pt8, on the one hand, and gates ps0 to ps3 and ps5 to ps8, on the other hand, are respectively controlled by conditions NO to N3 and N5 to N8, on the @e hand, and o the o ther hand, by their complements NO to N3 and N5 to N8. Thus, gate ptO becomes conducting by condition NO for the connection of the output ssl of circuit PS1 to conductor gsO, and gate ps0 becomes conducting by condition N0 for the direct connection of the output ss0 of circuit PS1 to conductor gs0. It is the same for gates ptl, ps1, pt2, ps2, p28, ps8.

When a failure appears in thgnetwork section SR3, it has been seen that condition N3 disappears and condition N3 appears and that consequently the data bit transmitted to the parity generator PEI on conductor ge3 was transmitted, by input equipment REl (FIG. 3) to the emergency section SR4. This bit is thus presented to the parity check circuit PS1 on conductor 651,. This circuit retransmits it on the output conductor ss4. As gate pt3 has become conducting by condition N3, it retransmits said bit on the output conductor gs3. Therefore, in case of failure in the network section SR3, the bit of the coded combinations normally transmitted by this section takes, in the network of FIG. 1, the emergency section SR4. This shift takes place simultaneously at the network inputs and outputs. At the inputs, it routes the bit of the coded combinations which should be transmitted by the faulty section SR3 onto the emergency section SR4; at the outputs, it performs the reverse switching in order to give to the bit supplied by the emergency section the place it has in each coded combination.

It will be now assumed that a failure has occurred in the network section SRO. Conditions N to IE disappear and conditions NO to N3 appear. Gates ps0 to p53 are disabled and gates p10 to pt3 become conducting. The outputs ssl to ss4 of the parity check circuit PS1 'are associated respectively with conductors gs0 to gs3 via the respective gates ptO to pt3.

Similarly, when a failure occurs in the network section SR5, condition W disappears and condition N5 appears. Gate ptS becomes conducting and gate ps5 is blocked. The output ss4 of the parity check circuit PS1 is associated with conductor gs5 via gate ptS.

It is now assumed that a failure occurs in the network section SR8; conditions N8 to N5 appear and the complementary conditions N 8 to g disappear. Gates p18 to ptS become conducting and gates 258 to ps5 become non-conducting. The outputs ss7 to ss4 of circuit PS1 are associated respectively with conductors gs8 to gsS via the respective gates p28 to pt5.

In conclusion, when a failure appears in a network section, if, in input equipment REl, the outputs of the parity generator PEI and the gates are physically arranged as in FIG. 3, the different transmission paths remain practically unchanged. Indeed, when a failure occurs in one network section, the faulty transmission path is replaced by the neighbouring path. The wellknown process, in which section SR4 is a common emergency section, necessitates a multiple at the input of this section, connected via additional control gates. This requirement deteriorates the electrical characteristics of the emergency path and, consequently the performances of the system which are determined by those of the worst path. This arrangement thus avoids the electric propagation problems due, in particular, to the multiple at the emergency section input. The same remarks apply to the circuits of output equipment RS1.

Now will be described, referring to FIG. 5, an embodiment of the decoding circuits making it possible to obtain thed ifferen tconditions N0 to N8 and their complements NO to N8 necessary to the operation of the circuits of FIGS. 3 and 4.

These decoding circuits, common to all multiplex groups include in particular a control circuit CLF. This circuit includes nine bistables bs0 to bs8. in the absence of failure, bistable bs4 is in position 1, the other bilables b ing res e t. The different output conductors bb0, bb0, bbl bbS of these bistables are associated with six OR gates dsl to ds3 and ds5 to ds7 as well as six AND gates dpl to dp3 and dpS to dp7; OR gate ds3 is thus associated with the direct outputs of bistables bs0 to bs3 and gate dp3 is associated with the complementary inputs of the same bistables. By giving to the output signals of the bistables the same references as the output conductors on which they appear, it may be written, N3 and 173 being respectively the output signals of gates ds3 and dp3:

2 3 ave N3 bbO bbl bb2 bb3 Analogous expressions describe the output signals N2/O and N2/() of gates ds2/O and dp2/O with:

W ET) The functions supplied by the outputs of OR gates ds/8 and AND gates dp5/8 will be expressed in the same way, from:

section SRO of the network of FIG. 1. The parity check circuit PS1 of output equipment RS1 of FIG. 4 detects this failure. It transmits the erroneous combinations on its output conductors ftl towards the control circuit CLF, which enables the identification of the faulty section. It is the same for each parity check circuit PS1 to PSn of all the output equipments of the switching center which detects an erroneous combination. The analysis of these erroneous combinations, for example by integration, will enable the identification of the network section in which is located the fault. Then, if it is section SRO, bistable bs4 and bistable bsO trigger, signal bb4 is no longer supplied and signal bb0 appearslhere results the disappearance of combinations N0/N3 and N4 and the appearance of combinations N0/N3.

It can be also assumed that a failure has appeared in section SR8 of the network in FIG. 1. In response, bistables bs4 and bsS of circuit CLF trigger. Signal bb8 appears and signal bb4 disappears. It results the appearance of combinat io n s lll8 to N5 and the disappearance of combinations N8/N5 and N4.

In summary, in the control circuit CLF, there is always one and one only bistable in position 1 which identifies the network section not to be used for the data bit transmission. The circuits of FIG. 5 then supply the conditions necessary to the input and output equipments of FIGS. 3 and 4.

Now referring to FIG. 6, will be described the operation of an input equipment enabling, in all cases, the check bit switching onto the faulty section, which facilitates, in particular, the identification of the faulty element of this section.

In FIG. 6, are found all the elements of FIG. 3 to which are added a set of 8 transfer gates pnO to pn3 and pnS to pnS. These gates are respectively controlled by the direct output signals bb0/bb3 and bb5/bb8 of bistables bs0/bs3 and bs5/bs8 of the control circuit CLF of FIG. 5. Thus, when signal bb3 appears, gate pn3 connects the output se4 of the parity generator PEl to conductor GE1 It is the same for the other gates pn0 It is assumed that a failure has appeared in one of sections SR8 of the network in FIG. 1. It has been seen that it results in the appearance of signal bb8 and in the disappearance of signal bb4 and, consequently, in the appearance of combinations N8 to N5 and in the disappearance of combinations N4 and fi /l afThe outputs se8 to seS of the parity generator are thus connected respectively to conductors GEl to GE1 The check bit is no longer transmitted by the output se4 to conductor GE 1 gate pe4 being blocked. But gate pn8 rendered conducting by signal bb8 routes the check bit on conductor GElg, towards section SR8.

It is obvious that the preceding description has only been given as an unrestrictive example and that numerous alternatives maybe considered without departing from the scope of the invention. In particular, all numerical details have been given only to facilitate the understanding of the invention and may vary with each application.

We claim:

1. A signal routing system in a switching network for transmitting coded signals in parallel, the system comprising switching means coupling each input to an output of the network, said system having n signal accesses arranged according to a certain order and n+1 network accesses also arranged according to a certain order and corresponding to n+1 network sections, as well as normal switching means associating, in rest condition, the n signal accesses with the n network accesses of corresponding ranks, the n+lth network access of rank p corresponding to the emergency section network, the signal routing system comprising onto emergency" switching means provided for associating, in case of failure in one network section of rank in, the signal accesses of ranks m to pl to the network accesses of ranks m+l to p, whereby each signal access is connected either to the network access of the same rank, at rest, or to the network access of the following rank, in case of failure, the signal transmission conditions remaining almost the same in both cases.

2. A signal routing system in a switching network for transmitting coded signals in parallel, the system comprising switching means coupling each input to an output of the network, said system having n signal accesses arranged according to a certain order and n+1 network accesses also arranged according to a certain order and corresponding to n+1 network sections, as well as two groups of normal switching means associating, in rest condition, signal accesses arranged from 0 to il and from i+l to n with network accesses of the same rank, an emergency section occupying a central position of rank i, the signal routing system comprising two groups of switching means onto emergency, those of the first group associating selectively the signal accesses of ranks O to il with the network accesses of ranks l to i, in case of failure in one of the network sections of ranks O to il and those of the second group associating selectively the signal accesses of ranks i+l to n with the network accesses of ranks i to nl in case of failure in one of the network sections of ranks i+l to n, thereby simplifying the design of the switching onto emergency control circuits. 

1. A signal routing system in a switching network for transmitting coded signals in parallel, the system comprising switching means coupling each input to an output of the network, said system having n signal accesses arranged according to a certain order and n+1 network accesses also arranged according to a certain order and corresponding to n+1 network sections, as well as normal switching means associating, in rest condition, the n signal accesses with the n network accesses of corresponding ranks, the n+1th network access of rank p corresponding to the emergency section network, the signal routing system comprising ''''onto emergency'''' switching means provided for associating, in case of failure in one network section of rank m, the signal accesses of ranks m to p-1 to the network accesses of ranks m+1 to p, whereby each signal access is connected either to the network access of the same rank, at rest, or to the network access of the following rank, in case of failure, the signal transmission conditions remaining almost the same in both cases.
 2. A signal routing system in a switching network for transmitting coded signals in parallel, the system comprising switching means coupling each input to an outpuT of the network, said system having n signal accesses arranged according to a certain order and n+1 network accesses also arranged according to a certain order and corresponding to n+1 network sections, as well as two groups of normal switching means associating, in rest condition, signal accesses arranged from 0 to i-1 and from i+1 to n with network accesses of the same rank, an emergency section occupying a central position of rank i, the signal routing system comprising two groups of switching means ''''onto emergency,'''' those of the first group associating selectively the signal accesses of ranks 0 to i-1 with the network accesses of ranks 1 to i, in case of failure in one of the network sections of ranks 0 to i-1 and those of the second group associating selectively the signal accesses of ranks i+1 to n with the network accesses of ranks i to n-1, in case of failure in one of the network sections of ranks i+1 to n, thereby simplifying the design of the ''''switching onto emergency'''' control circuits. 